Up  The Power-on circuit  

A power-on reset circuit generates a reset signal when power is applied, ensuring so that a system starts operating in a known state.

The HP-35 uses a simple POW circuit composed by a RC and a Shmitt trigger.  

The RC network charges with the PSU voltage rise and the Schmitt trigger is used to generates an impulse and to keep the INIT signal at logic 1 (0 volts). The length of this delay is not critical but lasts 25-30 milliseconds. 

This long delay (compared to the time word of the machine = 280 us) gives time to each of the 3 ROMS to be synchronized to the main system counter (SYNC is high during bit time window b45-b54).

At its end the state of the system is stable and INIT is at logic level 0 (+6v Vss), ROM 0 is active, ROM1 and ROM 2 are inactive, and the starting address “00000” is gated on line Ia (see below the schematics and 2 photos of the circuit on the main HP-35's PCB.  

 

fig 1, power on schematics

fig 2, power on circuit (photo D. Weed, 2007)


fig 3, power on commented schematics